1410 search results - page 159 / 282 » A Logic for Virtual Memory |
152
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INFOCOM
2012
IEEE
13 years 7 months ago
2012
IEEE
Packet classification is one of the major challenges in designing high-speed routers and firewalls as it involves sophisticated multi-dimensional searching. Ternary Content Address...
138
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EMSOFT
2007
Springer
15 years 8 months ago
2007
Springer
The soundness of device drivers generally cannot be verified in isolation, but has to take into account the reactions of the hardware devices. In critical embedded systems, interf...
150
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CF
2006
ACM
15 years 8 months ago
2006
ACM
This paper presents our experience mapping OpenMP parallel programming model to the IBM Cyclops-64 (C64) architecture. The C64 employs a many-core-on-a-chip design that integrates...
152
Voted
FPGA
2000
ACM
15 years 8 months ago
2000
ACM
A considerable portion of a chip is dedicated to a cache memory in a modern microprocessor chip. However, some applications may not actively need all the cache storage, especially...
145
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TCAD
2008
15 years 4 months ago
2008
Abstract--Multimedia and DSP applications have several computationally intensive kernels which are often offloaded and accelerated by application-specific hardware. This paper pres...