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» A Logical Viewpoint on Architectures
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ICCD
2007
IEEE
132views Hardware» more  ICCD 2007»
14 years 7 months ago
Post-layout comparison of high performance 64b static adders in energy-delay space
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
Sheng Sun, Carl Sechen
DSN
2009
IEEE
14 years 5 months ago
Decoupling Dynamic Information Flow Tracking with a dedicated coprocessor
Dynamic Information Flow Tracking (DIFT) is a promising security technique. With hardware support, DIFT prevents a wide range of attacks on vulnerable software with minimal perfor...
Hari Kannan, Michael Dalton, Christos Kozyrakis
ISMIS
2003
Springer
14 years 4 months ago
Enacting an Agent-Based Digital Self in a 24x7 Web Services World
As broadband access to the Internet becomes pervasive, the need for a 24 hours a day, seven days a week (24x7) interface within the client devices, requires a level of sophisticati...
Steve Goschnick
FCCM
1999
IEEE
146views VLSI» more  FCCM 1999»
14 years 3 months ago
Sepia: Scalable 3D Compositing Using PCI Pamette
We have implemented an image combining architecture that allows distributed rendering of a partitioned data set at interactive rates. The architecture achieves real-time frame rat...
Laurent Moll, Mark Shand, Alan Heirich
FPGA
1997
ACM
149views FPGA» more  FPGA 1997»
14 years 2 months ago
Signal Processing at 250 MHz Using High-Performance FPGA's
This paper describes an application in high-performance signal processing using reconfigurable computing engines: a 250 MHz cross-correlator for radio astronomy. Experimental resu...
Brian Von Herzen