ICCD 2007 - PDF Preprint Papers

ICCD 2007 International Conference on Computer Design

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ICCD
2007
IEEE

746views Hardware» more ICCD 2007»

Hardware design of a Binary Integer Decimal-based floating-point adder

14 years 8 months ago

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Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it are included in the IEEE Draft Standard for Floating-point Arithmetic (IEEE P75...

Charles Tsen, Sonia Gonzalez-Navarro, Michael J. S...

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Id	Views	Title	Status

1	746	Hardware design of a Binary Integer Decimal-based floating-point adder	claim
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4	225	Fine grain 3D integration for microarchitecture design through cube packing exploration	claim
5	215	A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS	claim
6	212	Analytical thermal placement for VLSI lifetime improvement and minimum performance variation	claim
7	206	SCAFFI: An intrachip FPGA asynchronous interface based on hard macros	claim
8	205	Hardware libraries: An architecture for economic acceleration in soft multi-core environments
9	200	A parallel IEEE P754 decimal floating-point multiplier	claim
10	195	LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation	claim
11	190	Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits	claim
12	183	Constraint satisfaction in incremental placement with application to performance optimization under power constraints	claim
13	182	Reducing leakage power in peripheral circuits of L2 caches	claim
14	180	Improving the reliability of on-chip data caches under process variations	claim
15	179	Energy-aware co-processor selection for embedded processors on FPGAs	claim
16	173	Twiddle factor transformation for pipelined FFT processing	claim
17	161	Scan chain design for three-dimensional integrated circuits (3D ICs)	claim
18	159	CMOS logic design with independent-gate FinFETs	claim
19	157	Limits on voltage scaling for caches utilizing fault tolerant techniques	claim
20	157	Combining cluster sampling with single pass methods for efficient sampling regimen design	claim
21	152	Compiler-assisted architectural support for program code integrity monitoring in application-specific instruction set processors	claim
22	151	Benchmarks and performance analysis of decimal floating-point applications	claim
23	150	CAP: Criticality analysis for power-efficient speculative multithreading	claim
24	149	A radix-10 SRT divider based on alternative BCD codings	claim
25	146	Exploring DRAM cache architectures for CMP server platforms	claim
26	145	Effective Dynamic Thermal Management for MPEG-4 decoding	claim
27	144	Application of symbolic computer algebra to arithmetic circuit verification	claim
28	141	Floating-point division algorithms for an x86 microprocessor with a rectangular multiplier	claim
29	140	A low overhead hardware technique for software integrity and confidentiality	claim
30	140	Continual hashing for efficient fine-grain state inconsistency detection	claim
31	139	Statistical simulation of chip multiprocessors running multi-program workloads	claim
32	139	Whitespace redistribution for thermal via insertion in 3D stacked ICs	claim
33	133	System level power estimation methodology with H.264 decoder prediction IP case study	claim
34	132	A position-insensitive finished store buffer	claim
35	132	Post-layout comparison of high performance 64b static adders in energy-delay space	claim
36	128	Contention-free switch-based implementation of 1024-point Radix-2 Fourier Transform Engine	claim
37	125	Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor	claim
38	125	Power variations of multi-port routers in an application-specific NoC design : A case study	claim
39	124	Placement and routing of RF embedded passive designs in LCP substrate	claim
40	121	Fast power network analysis with multiple clock domains	claim
41	120	Statistical timing analysis using Kernel smoothing	claim
42	111	On modeling impact of sub-wavelength lithography on transistors	claim
43	109	Improving cache efficiency via resizing + remapping	claim
44	106	Transparent mode flip-flops for collapsible pipelines	claim
45	105	Exploring the interplay of yield, area, and performance in processor caches	claim
46	105	Circuit-level mismatch modelling and yield optimization for CMOS analog circuits	claim
47	105	Power-aware mapping for reconfigurable NoC architectures	claim
48	100	VOSCH: Voltage scaled cache hierarchies	claim
49	99	Power reduction of chip multi-processors using shared resource control cooperating with DVFS	claim
50	98	Evaluating voltage islands in CMPs under process variations	claim
51	98	Priority-monotonic energy management for real-time systems with reliability requirements	claim
52	97	Automatic SystemC TLM generation for custom communication platforms	claim

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