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» A Logical Viewpoint on Architectures
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DAC
1998
ACM
13 years 12 months ago
Buffer Insertion for Noise and Delay Optimization
Interconnect-driven optimization is an increasingly important step in high-performance design. Algorithms for buffer insertion have been successfully utilized to reduce delay in gl...
Charles J. Alpert, Anirudh Devgan, Stephen T. Quay
CF
2006
ACM
13 years 11 months ago
Landing openMP on cyclops-64: an efficient mapping of openMP to a many-core system-on-a-chip
This paper presents our experience mapping OpenMP parallel programming model to the IBM Cyclops-64 (C64) architecture. The C64 employs a many-core-on-a-chip design that integrates...
Juan del Cuvillo, Weirong Zhu, Guang R. Gao
ARITH
2001
IEEE
13 years 11 months ago
Computer Arithmetic-A Processor Architect's Perspective
The Instruction Set Architecture (ISA) of a programmable processor is the native languageof the machine. It defines the set of operations and resourcesthat are optimized for that ...
Ruby B. Lee
FPGA
1995
ACM
118views FPGA» more  FPGA 1995»
13 years 11 months ago
An SBus Monitor Board
During the development of computer peripherals which interface to the processor via the system bus it is often necessary to acquire the signals on the bus at the hardware level. I...
H. A. Xie, Kevin E. Forward, K. M. Adams, D. Leask
AOSD
2008
ACM
13 years 10 months ago
Support for distributed adaptations in aspect-oriented middleware
Many aspect-oriented middleware platforms support run-time aspect weaving, but do not support coordinating distributed changes to a set of aspects at run-time. A distributed chang...
Eddy Truyen, Nico Janssens, Frans Sanen, Wouter Jo...