Sciweavers

1604 search results - page 310 / 321
» A Logical Viewpoint on Architectures
Sort
View
MICRO
2006
IEEE
84views Hardware» more  MICRO 2006»
14 years 1 months ago
Reunion: Complexity-Effective Multicore Redundancy
To protect processor logic from soft errors, multicore redundant architectures execute two copies of a program on separate cores of a chip multiprocessor (CMP). Maintaining identi...
Jared C. Smolens, Brian T. Gold, Babak Falsafi, Ja...
RTSS
2006
IEEE
14 years 1 months ago
Run-Time Services for Hybrid CPU/FPGA Systems on Chip
Modern FPGA devices, which include (multiple) processor core(s) as diffused IP on the silicon die, provide an excellent platform for developing custom multiprocessor systems-on-pr...
Jason Agron, Wesley Peck, Erik Anderson, David L. ...
IWCMC
2006
ACM
14 years 1 months ago
Modeling key agreement in multi-hop ad hoc networks
Securing multicast communications in ad hoc networks has become one of the most challenging research directions in the areas of wireless networking and security. This is especiall...
Giovanni Di Crescenzo, Maria Striki, John S. Baras
VEE
2006
ACM
155views Virtualization» more  VEE 2006»
14 years 1 months ago
A feather-weight virtual machine for windows applications
Many fault-tolerant and intrusion-tolerant systems require the ability to execute unsafe programs in a realistic environment without leaving permanent damages. Virtual machine tec...
Yang Yu, Fanglu Guo, Susanta Nanda, Lap-Chung Lam,...
FCCM
2005
IEEE
139views VLSI» more  FCCM 2005»
14 years 1 months ago
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation
Just-in-time (JIT) compilation has been used in many applications to enable standard software binaries to execute on different underlying processor architectures. We previously in...
Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan