MICRO 2006 - PDF Preprint Papers

MICRO 2006 IEEE/ACM International Symposium on Microarchitecture

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MICRO
2006
IEEE

191views Hardware» more MICRO 2006»

CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs

13 years 11 months ago

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Since processor performance scalability will now mostly be achieved through thread-level parallelism, there is a strong incentive to parallelize a broad range of applications, inc...

Pierre Palatin, Yves Lhuillier, Olivier Temam

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Id	Views	Title	Status

1	191	CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs	claim
2	162	Adaptive Caches: Effective Shaping of Cache Behavior to Workloads	claim
3	159	MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits	claim
4	155	In-Network Cache Coherence	claim
5	145	Virtually Pipelined Network Memory	claim
6	145	ASR: Adaptive Selective Replication for CMP Caches	claim
7	145	A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design	claim
8	144	Die Stacking (3D) Microarchitecture	claim
9	135	Support for High-Frequency Streaming in CMPs	claim
10	132	Scalable Cache Miss Handling for High Memory-Level Parallelism	claim
11	132	Data-Dependency Graph Transformations for Superblock Scheduling	claim
12	127	A Predictive Performance Model for Superscalar Processors	claim
13	124	LIFT: A Low-Overhead Practical Information Flow Tracking System for Detecting Security Attacks	claim
14	117	PathExpander: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection	claim
15	117	Coherence Ordering for Ring-based Chip Multiprocessors	claim
16	115	Mitigating the Impact of Process Variations on Processor Register Files and Execution Units	claim
17	115	Court Dismisses "Copyright Champion's" Source Code Copyright Suit	claim
18	114	Authentication Control Point and Its Implications For Secure Processor Design	claim
19	113	Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers	claim
20	111	Memory Prefetching Using Adaptive Stream Detection	claim
21	107	Dataflow Predication	claim
22	106	Wish Branches: Enabling Adaptive and Aggressive Predicated Execution	claim
23	105	Distributed Microarchitectural Protocols in the TRIPS Prototype Processor	claim
24	104	Leveraging Optical Technology in Future Bus-based Chip Multiprocessors	claim
25	103	NoSQ: Store-Load Communication without a Store Queue	claim
26	102	Managing Distributed, Shared L2 Caches through OS-Level Page Allocation	claim
27	100	Serialization-Aware Mini-Graphs: Performance with Fewer Resources	claim
28	98	ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers	claim
29	96	Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions	claim
30	96	Xbox 360 System Architecture	claim
31	94	Four nightmares for net neutrality	claim
32	94	A Sampling Method Focusing on Practicality	claim
33	90	Digitally Assisted Analog Circuits	claim
34	89	DMDC: Delayed Memory Dependence Checking through Age-Based Filtering	claim
35	89	Ubiquitous clicks and complements	claim
36	88	SWICH: A Prototype for Efficient Cache-Level Checkpointing and Rollback	claim
37	85	Legislating Entrepreneurship: An Oxymoron?	claim
38	84	Reunion: Complexity-Effective Multicore Redundancy	claim
39	82	Yield-Aware Cache Architectures	claim
40	80	New Jersey federal court holds Qualcomm's unFRANDly acts no antitrust violation	claim
41	79	Fair Queuing Memory Systems	claim
42	78	Fire-and-Forget: Load/Store Scheduling with No Store Queue at All	claim
43	74	Phoenix: Detecting and Recovering from Permanent Processor Design Bugs with Programmable Hardware	claim
44	73	Merging Head and Tail Duplication for Convergent Hyperblock Formation	claim
45	71	Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance	claim
46	68	Using STEAM for Thermal Simulation of Storage Systems	claim

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