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» A Low Power DSP Engine for Wireless Communications
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CGO
2004
IEEE
14 years 10 days ago
FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths
Application-specific instruction set processors (ASIPs) have the potential to meet the challenging cost, performance, and power goals of future embedded processors by customizing ...
Manjunath Kudlur, Kevin Fan, Michael L. Chu, Rajiv...
ICSE
2007
IEEE-ACM
14 years 8 months ago
A Robust Semantic Overlay Network for Microgrid Control Applications
Abstract. Control systems for electrical microgrids rely ever more on heterogeneous off-the-shelf technology for hardware, software and networking among the intelligent electronic ...
Geert Deconinck, Koen Vanthournout, Hakem Beitolla...
ARCS
2009
Springer
14 years 3 months ago
Ultra-Fast Downloading of Partial Bitstreams through Ethernet
Abstract. In this paper we present a partial bitstreams ultra-fast downloading process through a standard Ethernet network. These Virtex-based and partially reconfigurable systems...
Pierre Bomel, Jeremie Crenne, Linfeng Ye, Jean-Phi...
VSTTE
2005
Springer
14 years 2 months ago
Performance Validation on Multicore Mobile Devices
The validation of modern software systems on mobile devices needs to incorporate both functional and non-functional requirements. While some progress has been made in validating pe...
Thomas Hubbard, Raimondas Lencevicius, Edu Metz, G...
CODES
2006
IEEE
14 years 2 months ago
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
Martijn Coenen, Srinivasan Murali, Andrei Radulesc...