Sciweavers

389 search results - page 76 / 78
» A Model for the Coanalysis of Hardware and Software Architec...
Sort
View
PPOPP
2009
ACM
14 years 7 months ago
An efficient transactional memory algorithm for computing minimum spanning forest of sparse graphs
Due to power wall, memory wall, and ILP wall, we are facing the end of ever increasing single-threaded performance. For this reason, multicore and manycore processors are arising ...
Seunghwa Kang, David A. Bader
ODRL
2004
13 years 8 months ago
Nonius: Implementing a DRM Extension to an XML Browser
The paper describes experiences, ideas, and problems that were discovered while developing a digital rights management (DRM) extension to an XML browser. The supported rights desc...
Olli Pitkänen, Ville Saarinen, Jari Anttila, ...
DAC
2006
ACM
14 years 7 months ago
Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery
Modern integrated circuits (ICs) are becoming increasingly complex. The complexity makes it difficult to design, manufacture and integrate these high-performance ICs. The advent o...
Xinping Zhu, Wei Qin
PPOPP
2010
ACM
14 years 1 months ago
Load balancing on speed
To fully exploit multicore processors, applications are expected to provide a large degree of thread-level parallelism. While adequate for low core counts and their typical worklo...
Steven Hofmeyr, Costin Iancu, Filip Blagojevic
DSRT
2008
IEEE
13 years 8 months ago
RTPROC: A System for Rapid Real-Time Prototyping in Audio Signal Processing
In this contribution a new system for the rapid development of real-time prototypes for digital audio signal processing algorithms on Windows PCs and a Digital Signal Processor (D...
Hauke Krüger, Peter Vary