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DAC 2006 Design Automation Conference

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DAC
2006
ACM

245views Computer Architecture» more DAC 2006»

Are carbon nanotubes the future of VLSI interconnections?

15 years 12 days ago

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Increasing resistivity of copper with scaling and rising demands on current density requirements are driving the need to identify new wiring solutions for deep nanometer scale VLS...

Kaustav Banerjee, Navin Srivastava

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Id	Views	Title	Status

1	245	Are carbon nanotubes the future of VLSI interconnections?	claim
2	199	A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip	claim
3	197	Circuits for energy harvesting sensor signal processing	claim
4	195	Harvesting aware power management for sensor networks	claim
5	187	Behavior and communication co-optimization for systems with sequential communication media	claim
6	177	Stochastic variational analysis of large power grids considering intra-die correlations	claim
7	176	Statistical logic cell delay analysis using a current-based model	claim
8	169	An adaptive FPGA architecture with process variation compensation and reduced leakage	claim
9	169	Buffer memory optimization for video codec application modeled in Simulink	claim
10	168	Systematic temperature sensor allocation and placement for microprocessors	claim
11	166	Design automation for DNA self-assembled nanostructures	claim
12	165	DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip	claim
13	163	Architecture-aware FPGA placement using metric embedding	claim
14	163	Scheduling-based test-case generation for verification of multimedia SoCs	claim
15	163	Statistical timing based on incomplete probabilistic descriptions of parameter uncertainty	claim
16	162	Statistical timing analysis with correlated non-gaussian parameters using independent component analysis	claim
17	161	Programming models and HW-SW interfaces abstraction for multi-processor SoC	claim
18	160	BoxRouter: a new global router based on box expansion and progressive ILP	claim
19	159	NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture	claim
20	158	Automatic invariant strengthening to prove properties in bounded model checking	claim
21	156	Design space exploration using time and resource duality with the ant colony optimization	claim
22	155	High-level power management of embedded systems with application-specific energy cost functions	claim
23	154	Systematic software-based self-test for pipelined processors	claim
24	150	An efficient and versatile scheduling algorithm based on SDC formulation	claim
25	149	Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies	claim
26	149	High-performance operating system controlled memory compression	claim
27	148	Novel full-chip gridless routing considering double-via insertion	claim
28	148	Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction	claim
29	148	DFM: where's the proof of value?	claim
30	147	Early cutpoint insertion for high-level software vs. RTL formal combinational equivalence verification	claim
31	147	DAG-aware AIG rewriting a fresh look at combinational logic synthesis	claim
32	147	Modeling and minimization of PMOS NBTI effect for robust nanometer design	claim
33	146	Placement of digital microfluidic biochips using the t-tree formulation	claim
34	145	HybDTM: a coordinated hardware-software approach for dynamic thermal management	claim
35	145	Charge recycling in MTCMOS circuits: concept and analysis	claim
36	144	Optimal simultaneous mapping and clustering for FPGA delay optimization	claim
37	144	Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability	claim
38	144	Clock buffer and wire sizing using sequential programming	claim
39	143	SAT sweeping with local observability don't-cares	claim
40	141	Timing-based delay test for screening small delay defects	claim
41	141	Fast algorithms for slew constrained minimum cost buffering	claim
42	140	GreenBus: a generic interconnect fabric for transaction level modelling	claim
43	140	Prototyping a fault-tolerant multiprocessor SoC with run-time fault recovery	claim
44	139	Formal analysis of hardware requirements	claim
45	139	Fast analysis of structured power grid by triangularization based structure preserving model order reduction	claim
46	138	Efficient detection and exploitation of infeasible paths for software timing analysis	claim
47	135	Optimality study of resource binding with multi-Vdds	claim
48	134	SystemC transaction level models and RTL verification	claim
49	133	A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy	claim
50	133	MARS-C: modeling and reduction of soft errors in combinational circuits	claim
51	133	Systems for human-powered mobile computing	claim
52	132	Synthesis of synchronous elastic architectures	claim
53	132	An automated, reconfigurable, low-power RFID tag	claim
54	132	Criticality computation in parameterized statistical timing	claim
55	131	Automated design of pin-constrained digital microfluidic arrays for lab-on-a-chip applications*	claim
56	130	Gate sizing: finFETs vs 32nm bulk MOSFETs	claim
57	130	Predicate learning and selective theory deduction for a difference logic solver	claim
58	130	Hierarchical power distribution and power management scheme for a single chip mobile processor	claim
59	129	State encoding of large asynchronous controllers	claim
60	129	Rapid and low-cost context-switch through embedded processor customization for real-time and control applications	claim
61	129	Extending the lifetime of fuel cell based hybrid systems	claim
62	129	A high density, carbon nanotube capacitor for decoupling applications	claim
63	129	Minimization for LED-backlit TFT-LCDs	claim
64	129	IMPRES: integrated monitoring for processor reliability and security	claim
65	128	Reliability challenges for 45nm and beyond	claim
66	128	A fast on-chip decoupling capacitance budgeting algorithm using macromodeling and linear programming	claim
67	126	Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming	claim
68	126	Signature-based workload estimation for mobile 3D graphics	claim
69	125	Building a verification test plan: trading brute force for finesse	claim
70	124	Process variation aware OPC with variational lithography modeling	claim
71	123	Games are up for DVFS	claim
72	123	Gain-based technology mapping for minimum runtime leakage under input vector uncertainty	claim
73	121	Refined statistical static timing analysis through	claim
74	120	A design approach for radiation-hard digital electronics	claim
75	120	An efficient retiming algorithm under setup and hold constraints	claim
76	120	Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration	claim
77	120	Optimal jumper insertion for antenna avoidance under ratio upper-bound	claim
78	120	Mining global constraints for improving bounded sequential equivalence checking	claim
79	119	Exploiting forwarding to improve data bandwidth of instruction-set extensions	claim
80	117	How will the fabless model survive?	claim
81	116	Transistor abstraction for the functional verification of FPGAs	claim
82	116	Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing	claim
83	116	Shielding against design flaws with field repairable control logic	claim
84	116	Elmore model for energy estimation in RC trees	claim
85	115	Practical methods in coverage-oriented verification of the merom microprocessor	claim
86	115	Exploring compromises among timing, power and temperature in three-dimensional integrated circuits	claim
87	115	Backlight dimming in power-aware mobile displays	claim
88	115	Constraint-driven floorplan repair	claim
89	115	Guiding simulation with increasingly refined abstract traces	claim
90	115	Use of C/C++ models for architecture exploration and verification of DSPs	claim
91	114	Modeling and analysis of circuit performance of ballistic CNFET	claim
92	114	A CMOS SoC for 56/18/16 CD/DVD-dual/RAM applications	claim
93	114	"The IC nanometer race -- what will it take to win?"	claim
94	113	Communication latency aware low power NoC synthesis	claim
95	113	Leakage power reduction of embedded memories on FPGAs through location assignment	claim
96	112	A novel variation-aware low-power keeper architecture for wide fan-in dynamic gates	claim
97	112	A new LP based incremental timing driven placement for high performance designs	claim
98	112	Prediction-based flow control for network-on-chip traffic	claim
99	112	A new hybrid FPGA with nanoscale clusters and CMOS routing	claim
100	112	SMERT: energy-efficient design of a multimedia messaging system for mobile devices	claim
101	111	Exploring trade-offs in buffer requirements and throughput constraints for synchronous dataflow graphs	claim
102	111	Visibility enhancement for silicon debug	claim
103	110	Circuit simulation based obstacle-aware Steiner routing	claim
104	110	A reconfigurable design-for-debug infrastructure for SoCs	claim
105	109	Timing driven power gating	claim
106	109	Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM	claim
107	109	FLAW: FPGA lifetime awareness	claim
108	109	Energy-scalable OFDM transmitter design and control	claim
109	108	Power-centric design of high-speed I/Os	claim
110	108	Optimal cell flipping in placement and floorplanning	claim
111	107	Timing-driven Steiner trees are (practically) free	claim
112	107	Low-power bus encoding using an adaptive hybrid algorithm	claim
113	107	Design space exploration and prototyping for on-chip multimedia applications	claim
114	107	Efficient SAT-based Boolean matching for FPGA technology mapping	claim
115	106	Variation-aware analysis: savior of the nanometer era?	claim
116	105	Standard cell characterization considering lithography induced variations	claim
117	105	A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction	claim
118	104	Unknown-tolerance analysis and test-quality control for test response compaction using space compactors	claim
119	104	Design tools for reliability analysis	claim
120	104	Synthesis of high-performance packet processing pipelines	claim
121	104	A real time budgeting method for module-level-pipelined bus based system using bus scenarios	claim
122	103	A multi-port current source model for multiple-input switching effects in CMOS library cells	claim
123	102	Maintaining consistency between systemC and RTL system designs	claim
124	101	Topology aware mapping of logic functions onto nanowire-based crossbar architectures	claim
125	100	A parallelized way to provide data encryption and integrity checking on a processor-memory bus	claim
126	100	Entering the hot zone: can you handle the heat and be cool?	claim
127	98	Register binding for clock period minimization	claim
128	98	The zen of nonvolatile memories	claim
129	97	Steiner network construction for timing critical nets	claim
130	96	Rapid estimation of control delay from high-level specifications	claim
131	94	Electronics beyond nano-scale CMOS	claim
132	93	Efficient simulation of critical synchronous dataflow graphs	claim
133	92	Design in reliability for communication designs	claim
134	84	A family of cells to reduce the soft-error-rate in ternary-CAM	claim
135	83	Practical aspects of reliability analysis for IC designs	claim
136	82	Towards the automatic exploration of arithmetic-circuit architectures	claim
137	81	Tomorrow's analog: just dead or just different?	claim
138	78	A systematic method for functional unit power estimation in microprocessors	claim

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