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» A Network Fabric for Scalable Multiprocessor Systems
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INFOCOM
2005
IEEE
14 years 1 months ago
Practical algorithms for performance guarantees in buffered crossbars
— This paper is about high capacity switches and routers that give guaranteed throughput, rate and delay guarantees. Many routers are built using input queueing or combined input...
Shang-Tse Chuang, Sundar Iyer, Nick McKeown
AICCSA
2005
IEEE
124views Hardware» more  AICCSA 2005»
14 years 1 months ago
On multicast scheduling and routing in multistage Clos networks
Multicast communication, which involves transmitting information from one node to multiple nodes, is a vital operation in both broadband integrated services digital networks (BISD...
Bin Tang
ARC
2010
Springer
186views Hardware» more  ARC 2010»
13 years 11 months ago
Application-Specific Signatures for Transactional Memory in Soft Processors
As reconfigurable computing hardware and in particular FPGA-based systems-on-chip comprise an increasing number of processor and accelerator cores, supporting sharing and synchroni...
Martin Labrecque, Mark Jeffrey, J. Gregory Steffan
CCECE
2006
IEEE
14 years 1 months ago
QOS Driven Network-on-Chip Design for Real Time Systems
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya
HPCA
2009
IEEE
14 years 8 months ago
Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Reetuparna Das, Soumya Eachempati, Asit K. Mishra,...