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» A Network Memory Architecture Model and Performance Analysis
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IPPS
2002
IEEE
14 years 2 months ago
System-Level Analysis for MPEG-4 Decoding on a Multi-Processor Architecture
The convergence of TV and new features such as Internet and games, requires a generic media-processing platform, that enables simultaneous execution of very diverse tasks, ranging...
Egbert G. T. Jaspers, Erik B. van der Tol, Peter H...
IEEESCC
2006
IEEE
14 years 3 months ago
Memory Servers: A Scope of SOA for High-End Computing
The expanding gap between microprocessor and disk performance has initiated new techniques of providing memory as a service in high-end computing (HEC). Although the processor and...
Surendra Byna, Xian-He Sun, Ryan Nakhoul
TWC
2008
125views more  TWC 2008»
13 years 9 months ago
Packet level performance analysis in wireless user-relaying networks
In this paper, the impact of user relaying on the behavior of a relay node, which acts as the source node at the same time, is analyzed in a wireless relay network at the packet le...
Jun Cai, Attahiru Sule Alfa, Pinyi Ren, Xuemin She...
IEEEPACT
2009
IEEE
14 years 3 months ago
Interprocedural Load Elimination for Dynamic Optimization of Parallel Programs
Abstract—Load elimination is a classical compiler transformation that is increasing in importance for multi-core and many-core architectures. The effect of the transformation is ...
Rajkishore Barik, Vivek Sarkar
ACISICIS
2005
IEEE
14 years 2 months ago
Performance Analysis on Mobility of Ad-Hoc Network for Inter-Vehicle Communication
This paper presents the feasibility of using an ad-hoc network as an infrastructure for a small group of inter-vehicle communication network. Mobile ad-hoc networking with wireles...
Jaehyun Kim, Woojin Han, Woohyuk Choi, Yunil Hwang...