IEEEPACT 2009 - PDF Preprint Papers

IEEEPACT 2009 International Conference on Parallel Architectures and Compilation Techniques

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IEEEPACT
2009
IEEE

237views Distributed And Parallel Com...» more IEEEPACT 2009»

Polyhedral-Model Guided Loop-Nest Auto-Vectorization

14 years 7 months ago

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Abstract—Optimizing compilers apply numerous interdependent optimizations, leading to the notoriously difﬁcult phase-ordering problem — that of deciding which transformations...

Konrad Trifunovic, Dorit Nuzman, Albert Cohen, Aya...

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Id	Views	Title	Status

1	237	Polyhedral-Model Guided Loop-Nest Auto-Vectorization	claim
2	231	Cache Sharing Management for Performance Fairness in Chip Multiprocessors	claim
3	219	Automatic Tuning of Discrete Fourier Transforms Driven by Analytical Modeling	claim
4	212	Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors	claim
5	211	Anaphase: A Fine-Grain Thread Decomposition Scheme for Speculative Multithreading	claim
6	210	Analytical Modeling of Pipeline Parallelism	claim
7	185	Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors	claim
8	184	Using Aggressor Thread Information to Improve Shared Cache Management for CMPs	claim
9	183	Chainsaw: Using Binary Matching for Relative Instruction Mix Comparison	claim
10	178	Architecture Support for Improving Bulk Memory Copying and Initialization Performance	claim
11	176	SOS: A Software-Oriented Distributed Shared Cache Management Approach for Chip Multiprocessors	claim
12	175	FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery	claim
13	168	Region Based Structure Layout Optimization by Selective Data Copying	claim
14	166	Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading	claim
15	164	Soft-OLP: Improving Hardware Cache Performance through Software-Controlled Object-Level Partitioning	claim
16	157	StealthTest: Low Overhead Online Software Testing Using Transactional Memory	claim
17	147	Algorithmic Skeletons within an Embedded Domain Specific Language for the CELL Processor	claim
18	146	Flextream: Adaptive Compilation of Streaming Applications for Heterogeneous Architectures	claim
19	146	Core-Selectability in Chip Multiprocessors	claim
20	145	SHIP: Scalable Hierarchical Power Control for Large-Scale Data Centers	claim
21	142	Adaptive Locks: Combining Transactions and Locks for Efficient Concurrency	claim
22	136	ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs	claim
23	135	CPROB: Checkpoint Processing with Opportunistic Minimal Recovery	claim
24	129	Oblivious Routing in On-Chip Bandwidth-Adaptive Networks	claim
25	128	Quantifying the Potential of Program Analysis Peripherals	claim
26	127	Interprocedural Load Elimination for Dynamic Optimization of Parallel Programs	claim
27	118	DDCache: Decoupled and Delegable Cache Data and Metadata	claim
28	97	Zero-Value Caches: Cancelling Loads that Return Zero	claim

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