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» A Network Memory Architecture Model and Performance Analysis
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IPPS
2006
IEEE
14 years 3 months ago
Performance evaluation of wormhole routed network processor-memory interconnects
Network line cards are experiencing ever increasing line rates, random data bursts, and limited space. Hence, they are more vulnerable than other processormemory environments, to ...
Taskin Koçak, Jacob Engel
PODC
2009
ACM
14 years 6 months ago
Memory models: a case for rethinking parallel languages and hardware
The era of parallel computing for the masses is here, but writing correct parallel programs remains far more difficult than writing sequential programs. Aside from a few domains,...
Sarita V. Adve
CONEXT
2007
ACM
14 years 1 months ago
On the cost of caching locator/ID mappings
Very recent activities in the IETF and in the Routing Research Group (RRG) of the IRTG focus on defining a new Internet architecture, in order to solve scalability issues related ...
Luigi Iannone, Olivier Bonaventure
HPDC
1996
IEEE
14 years 1 months ago
Shared Memory NUMA Programming on I-WAY
The performance of the Global Array shared-memory nonuniform memory-access programming model is explored on the I-WAY, wide-area-network distributed supercomputer environment. The...
Jarek Nieplocha, Robert J. Harrison
CONEXT
2006
ACM
14 years 3 months ago
Proposition of a cross-layer architecture model for the support of QoS in ad-hoc networks
Due to the lack of built-in quality of service support, IEEE 802.11 ad-hoc networks presents serious defies in meeting the demands of multimedia applications. To overcome such ch...
Wafa Berrayana, Habib Youssef, Stéphane Loh...