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» A Network Memory Architecture Model and Performance Analysis
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ITIIS
2008
128views more  ITIIS 2008»
13 years 9 months ago
An Asymmetric Key-Based Security Architecture for Wireless Sensor Networks
In spite of previous common assumptions about the incompatibility of public key cryptography (PKC) schemes with wireless sensor networks (WSNs), recent works have shown that they ...
Md. Mokammel Haque, Al-Sakib Khan Pathan, Choong S...
DAC
2008
ACM
14 years 10 months ago
Study of the effects of MBUs on the reliability of a 150 nm SRAM device
1 Soft errors induced by radiation are an increasing problem in the microelectronic field. Although traditional models estimate the reliability of memories suffering Single Event U...
Juan Antonio Maestro, Pedro Reviriego
ICPP
2007
IEEE
14 years 3 months ago
RECN-IQ: A Cost-Effective Input-Queued Switch Architecture with Congestion Management
As the number of computing and storage nodes keeps increasing, the interconnection network is becoming a key element of many computing and communication systems, where the overall...
Gaspar Mora, Pedro Javier García, Jose Flic...
DSD
2008
IEEE
136views Hardware» more  DSD 2008»
14 years 3 months ago
Network Interface Sharing Techniques for Area Optimized NoC Architectures
Although preliminary analysis frameworks point out the performance speed-ups achievable by on-chip networks with respect to state-of-the-art interconnects, the area concern remain...
Alberto Ferrante, Simone Medardoni, Davide Bertozz...
IWMM
2011
Springer
270views Hardware» more  IWMM 2011»
13 years 2 days ago
Memory management in NUMA multicore systems: trapped between cache contention and interconnect overhead
Multiprocessors based on processors with multiple cores usually include a non-uniform memory architecture (NUMA); even current 2-processor systems with 8 cores exhibit non-uniform...
Zoltan Majo, Thomas R. Gross