Sciweavers

3629 search results - page 157 / 726
» A Network Memory Architecture Model and Performance Analysis
Sort
View
QEST
2006
IEEE
14 years 3 months ago
Modeling Fiber Delay Loops in an All Optical Switch
We analyze the effect of a few fiber delay loops on the number of deflections in an all optical packet switch. The switch is based on the ROMEO architecture developed by Alcatel...
Ana Busic, Mouad Ben Mamoun, Jean-Michel Fourneau
IAT
2010
IEEE
13 years 7 months ago
A Biologically-Inspired Cognitive Agent Model Integrating Declarative Knowledge and Reinforcement Learning
Abstract--The paper proposes a biologically-inspired cognitive agent model, known as FALCON-X, based on an integration of the Adaptive Control of Thought (ACT-R) architecture and a...
Ah-Hwee Tan, Gee Wah Ng
IEEEPACT
2008
IEEE
14 years 3 months ago
Leveraging on-chip networks for data cache migration in chip multiprocessors
Recently, chip multiprocessors (CMPs) have arisen as the de facto design for modern high-performance processors, with increasing core counts. An important property of CMPs is that...
Noel Eisley, Li-Shiuan Peh, Li Shang
MOBIHOC
2008
ACM
14 years 8 months ago
The networking shape of vehicular mobility
Mobility is the distinguishing feature of vehicular networks, affecting the evolution of network connectivity over space and time in a unique way. Connectivity dynamics, in turn, ...
Marco Fiore, Jérôme Härri
VISUALIZATION
1994
IEEE
14 years 1 months ago
Parallel Performance Measures for Volume Ray Casting
We describe a technique for achieving fast volume ray casting on parallel machines, using a load balancing scheme and an e cient pipelined approach to compositing. We propose a ne...
Cláudio T. Silva, Arie E. Kaufman