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» A Network Memory Architecture Model and Performance Analysis
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IPPS
2005
IEEE
14 years 1 months ago
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport
As semiconductor feature sizes decrease, interconnect delay is becoming a dominant component of processor cycle times. This creates a critical need to shift microarchitectural des...
Hongkyu Kim, D. Scott Wills, Linda M. Wills
ICDAR
2011
IEEE
12 years 7 months ago
A Digital Ink Recogntion Server for Handwritten Japanese Text
— This paper describes the design and implementation of a digital ink recognition server for handwritten Japanese text. Currently, fast and accurate recognition of online handwri...
Daqing Wang, Bilan Zhu, Masaki Nakagawa
SIGMETRICS
2010
ACM
214views Hardware» more  SIGMETRICS 2010»
14 years 15 days ago
Distributed sensor network localization from local connectivity: performance analysis for the HOP-TERRAIN algorithm
This paper addresses the problem of determining the node locations in ad-hoc sensor networks when only connectivity information is available. In previous work, we showed that the ...
Amin Karbasi, Sewoong Oh
NN
1998
Springer
108views Neural Networks» more  NN 1998»
13 years 7 months ago
How embedded memory in recurrent neural network architectures helps learning long-term temporal dependencies
Learning long-term temporal dependencies with recurrent neural networks can be a difficult problem. It has recently been shown that a class of recurrent neural networks called NA...
Tsungnan Lin, Bill G. Horne, C. Lee Giles
VLSID
2008
IEEE
191views VLSI» more  VLSID 2008»
14 years 2 months ago
Programming and Performance Modelling of Automotive ECU Networks
The last decade has seen a phenomenal increase in the use of electronic components in automotive systems, resulting in the replacement of purely mechanical or hydraulic-implementa...
Samarjit Chakraborty, Sethu Ramesh