Sciweavers

3629 search results - page 29 / 726
» A Network Memory Architecture Model and Performance Analysis
Sort
View
ISCA
1995
IEEE
118views Hardware» more  ISCA 1995»
13 years 11 months ago
The EM-X Parallel Computer: Architecture and Basic Performance
Latency tolerance is essential in achieving high performance on parallel computers for remote function calls and fine-grained remote memory accesses. EM-X supports interprocessor ...
Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Ha...
EAGC
2004
Springer
13 years 11 months ago
SCALEA-G: A Unified Monitoring and Performance Analysis System for the Grid
Abstract. This paper describes SCALEA-G, a unified monitoring and performance analysis system for the Grid. SCALEA-G is implemented as a set of grid services based on the Open Grid...
Hong Linh Truong, Thomas Fahringer
CODES
2006
IEEE
14 years 1 months ago
Integrated analysis of communicating tasks in MPSoCs
Predicting timing behavior is key to efficient embedded real-time system design and verification. Especially memory accesses and co-processor calls over shared communication net...
Simon Schliecker, Matthias Ivers, Rolf Ernst
IEICET
2007
42views more  IEICET 2007»
13 years 7 months ago
Scenario-Aware Bus Functional Modeling for Architecture-Level Performance Analysis
Eui-Young Chung, Hyuk-Jun Lee, Sung Woo Chung
ICWN
2008
13 years 9 months ago
A Finite Queue Model Analysis of PMRC-based Wireless Sensor Networks
In our previous work, a highly scalable and faulttolerant network architecture, the Progressive Multi-hop Rotational Clustered (PMRC) structure, is proposed for constructing large...
Qiaoqin Li, Mei Yang, Hongyan Wang, Yingtao Jiang,...