3629 search results - page 41 / 726 » A Network Memory Architecture Model and Performance Analysis |
129
Voted
ISCAS
2006
IEEE
15 years 9 months ago
2006
IEEE
Abstract— Shared memory is a common inter-processor communication paradigm for on-chip multiprocessor SoC (MPSoC) platforms. The latency overhead of switch-based interconnection ...
141
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PCI
2005
Springer
15 years 9 months ago
2005
Springer
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
116
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IPPS
2008
IEEE
15 years 10 months ago
2008
IEEE
With the emergence of multicore network processors in support of high-performance computing and networking applications, power consumption has become a problem of increasing signi...
125
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ICON
2007
IEEE
15 years 9 months ago
2007
IEEE
— Within packet processing systems, lengthy memory accesses greatly reduce performance. To overcome this limitation, network processors utilize many different techniques, e.g., u...