Sciweavers

3629 search results - page 42 / 726
» A Network Memory Architecture Model and Performance Analysis
Sort
View
WMPI
2004
ACM
15 years 9 months ago
Understanding the effects of wrong-path memory references on processor performance
High-performance out-of-order processors spend a significant portion of their execution time on the incorrect program path even though they employ aggressive branch prediction al...
Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale ...
MSN
2007
Springer
187views Sensor Networks» more  MSN 2007»
15 years 10 months ago
Performance Analysis of IEEE 802.11 in Multi-hop Wireless Networks
Abstract. Multi-hop wireless networks provide a quick and easy way for networking when we need a temporary network or when cabling is difficult. The 802.11 Medium Access Control (M...
Lan Tien Nguyen, Razvan Beuran, Yoichi Shinoda
130
Voted
PPOPP
2003
ACM
15 years 9 months ago
User-controllable coherence for high performance shared memory multiprocessors
In programming high performance applications, shared address-space platforms are preferable for fine-grained computation, while distributed address-space platforms are more suita...
Collin McCurdy, Charles N. Fischer
195
Voted
ISCA
1997
IEEE
137views Hardware» more  ISCA 1997»
15 years 8 months ago
VM-Based Shared Memory on Low-Latency, Remote-Memory-Access Networks
Recent technological advances have produced network interfaces that provide users with very low-latency access to the memory of remote machines. We examine the impact of such netw...
Leonidas I. Kontothanassis, Galen C. Hunt, Robert ...
163
Voted
SPAA
1995
ACM
15 years 7 months ago
Accounting for Memory Bank Contention and Delay in High-Bandwidth Multiprocessors
For years, the computation rate of processors has been much faster than the access rate of memory banks, and this divergence in speeds has been constantly increasing in recent yea...
Guy E. Blelloch, Phillip B. Gibbons, Yossi Matias,...