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» A Network Memory Architecture Model and Performance Analysis
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ASAP
2003
IEEE
133views Hardware» more  ASAP 2003»
14 years 1 months ago
Storage Management in Process Networks using the Lexicographically Maximal Preimage
At the Leiden Embedded Research Center, we are developing a compiler called Compaan that automatically translates signal processing applications written in Matlab into Kahn Proces...
Alexandru Turjan, Bart Kienhuis
IISWC
2008
IEEE
14 years 2 months ago
A workload for evaluating deep packet inspection architectures
—High-speed content inspection of network traffic is an important new application area for programmable networking systems, and has recently led to several proposals for high-per...
Michela Becchi, Mark A. Franklin, Patrick Crowley
ISCAS
2003
IEEE
172views Hardware» more  ISCAS 2003»
14 years 1 months ago
Performance modeling of resonant tunneling based RAMs
Tunneling based random-access memories (TRAM’s) have recently garnered a great amount of interests among the memory designers due to their intrinsic merits such as reduced power...
Hui Zhang, Pinaki Mazumder, Li Ding 0002, Kyoungho...
SIGMETRICS
2010
ACM
145views Hardware» more  SIGMETRICS 2010»
13 years 2 months ago
Towards architecture independent metrics for multicore performance analysis
The prevalence of multicore architectures has made the performance analysis of multithreaded applications an intriguing area of inquiry. An understanding of locality effects and c...
Milind Kulkarni, Vijay S. Pai, Derek L. Schuff
IPPS
2002
IEEE
14 years 20 days ago
Variable Partitioning and Scheduling of Multiple Memory Architectures for DSP
Multiple memory module architecture enjoys higher memory access bandwidth and thus higher performance. Two key problems in gaining high performance in this kind of architecture ar...
Qingfeng Zhuge, Bin Xiao, Edwin Hsing-Mean Sha