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» A Network Memory Architecture Model and Performance Analysis
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DAC
2007
ACM
14 years 8 months ago
Compact State Machines for High Performance Pattern Matching
Pattern matching is essential to a wide range of applications such as network intrusion detection, virus scanning, etc. Pattern matching algorithms normally rely on state machines...
Piti Piyachon, Yan Luo
IPPS
2000
IEEE
14 years 4 days ago
Support for Recoverable Memory in the Distributed Virtual Communication Machine
The Distributed Virtual Communication Machine (DVCM) is a software communication architecture for clusters of workstations equipped with programmable network interfaces (NIs) for ...
Marcel-Catalin Rosu, Karsten Schwan
DAC
2004
ACM
14 years 8 months ago
An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory
Massive data transfer encountered in emerging multimedia embedded applications requires architecture allowing both highly distributed memory structure and multiprocessor computati...
Sang-Il Han, Amer Baghdadi, Marius Bonaciu, Soo-Ik...
TII
2010
124views Education» more  TII 2010»
13 years 2 months ago
Address-Independent Estimation of the Worst-case Memory Performance
Abstract--Real-time systems are subject to temporal constraints and require a schedulability analysis to ensure that task execution finishes within lower and upper specified bounds...
Basilio B. Fraguela, Diego Andrade, Ramon Doallo
ICASSP
2011
IEEE
12 years 11 months ago
A methodology based on Transportation problem modeling for designing parallel interleaver architectures
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...
Awais Sani, Philippe Coussy, Cyrille Chavet, Eric ...