3629 search results - page 81 / 726 » A Network Memory Architecture Model and Performance Analysis |
IISWC
2006
IEEE
14 years 1 months ago
2006
IEEE
— As x86-64 processors become the CPU of choice for the personal computer market, it becomes increasingly important to understand the performance we can expect by migrating appli...
APLAS
2011
ACM
12 years 7 months ago
2011
ACM
Modern multi-core microprocessors implement weak memory consistency models; programming for these architectures is a challenge. This paper solves a problem open for ten years, and ...
CLUSTER
2008
IEEE
14 years 2 months ago
2008
IEEE
—User-level communication allows an application process to access the network interface directly. Bypassing the kernel requires that a user process accesses the network interface...
CF
2004
ACM
14 years 1 months ago
2004
ACM
The ever increasing gap between processor and memory speed, sometimes referred to as the Memory Wall problem [42], has a very negative impact on performance. This mismatch will be...
TC
2008
13 years 7 months ago
2008
On-chip interconnection networks (OCINs) have emerged as a modular and scalable solution for wire delay constraints in deep submicron VLSI design. OCIN research has shown that the ...