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» A Network Memory Architecture Model and Performance Analysis
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IPPS
2010
IEEE
13 years 6 months ago
Efficient hardware support for the Partitioned Global Address Space
We present a novel architecture of a communication engine for non-coherent distributed shared memory systems. The shared memory is composed by a set of nodes exporting their memory...
Holger Fröning, Heiner Litz
SIGGRAPH
2000
ACM
14 years 1 months ago
Pomegranate: a fully scalable graphics architecture
Pomegranate is a parallel hardware architecture for polygon rendering that provides scalable input bandwidth, triangle rate, pixel rate, texture memory and display bandwidth while...
Matthew Eldridge, Homan Igehy, Pat Hanrahan
MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
14 years 3 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
DTJ
1998
171views more  DTJ 1998»
13 years 8 months ago
Measurement and Analysis of C and C++ Performance
ir increasing use of abstraction, modularity, delayed binding, polymorphism, and source reuse, especially when these attributes are used in combination. Modern processor architectu...
Hemant G. Rotithor, Kevin W. Harris, Mark W. Davis
NETWORKING
2008
13 years 10 months ago
Cache Placement Optimization in Hierarchical Networks: Analysis and Performance Evaluation
Caching popular content in the Internet has been recognized as one of the effective solution to alleviate network congestion and accelerate user information access. Sharing and coo...
Wenzhong Li, Edward Chan, Yilin Wang, Daoxu Chen, ...