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» A New Pipelined Array Architecture for Signed Multiplication
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DAC
2007
ACM
14 years 8 months ago
Optimization of Area in Digital FIR Filters using Gate-Level Metrics
In the paper, we propose a new metric for the minimization of area in the generic problem of multiple constant multiplications, and demonstrate its effectiveness for digital FIR f...
Eduardo A. C. da Costa, José C. Monteiro, L...
IAJIT
2010
193views more  IAJIT 2010»
13 years 6 months ago
Performance of OCDMA Systems Using Random Diagonal Code for Different Decoders Architecture Schemes
: In this paper, new code families are constructed for spectral-amplitude coding optical code division multiple access, called random diagonal code for spectral amplitude coding op...
Hilal Adnan Fadhil, Syed Alwee Aljunid, Badlished ...
FPGA
2006
ACM
117views FPGA» more  FPGA 2006»
13 years 11 months ago
Context-free-grammar based token tagger in reconfigurable devices
In this paper, we present reconfigurable hardware architecture for detecting semantics of streaming data on 1+ Gbps networks. The design leverages on the characteristics of contex...
Young H. Cho, James Moscola, John W. Lockwood
HPCA
2008
IEEE
14 years 8 months ago
FlexiTaint: A programmable accelerator for dynamic taint propagation
This paper presents FlexiTaint, a hardware accelerator for dynamic taint propagation. FlexiTaint is implemented as an in-order addition to the back-end of the processor pipeline, ...
Guru Venkataramani, Ioannis Doudalis, Yan Solihin,...
ISPAN
2005
IEEE
14 years 1 months ago
An FPGA-Based Floating-Point Jacobi Iterative Solver
Within the parallel computing domain, field programmable gate arrays (FPGA) are no longer restricted to their traditional role as substitutes for application-specific integrated...
Gerald R. Morris, Viktor K. Prasanna