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» A Non-binary Parallel Arithmetic Architecture
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IEEEPACT
1998
IEEE
14 years 3 months ago
Athapascan-1: On-Line Building Data Flow Graph in a Parallel Language
In order to achieve practical efficient execution on a parallel architecture, a knowledge of the data dependencies related to the application appears as the key point for building...
François Galilée, Jean-Louis Roch, G...
SIGARCH
2010
89views more  SIGARCH 2010»
13 years 5 months ago
Efficient reconfigurable design for pricing asian options
Arithmetic Asian options are financial derivatives which have the feature of path-dependency: they depend on the entire price path of the underlying asset, rather than just the in...
Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, ...
ESTIMEDIA
2004
Springer
14 years 4 months ago
A hardware accelerator IP for EBCOT Tier-1 coding in JPEG2000 Standard
We proposed a hardware accelerator IP for the Tier-1 portion of Embedded Block Coding with Optimal Truncation (EBCOT) used in the JPEG2000 next generation image compression standa...
Tien-Wei Hsieh, Youn-Long Lin
HICSS
1995
IEEE
109views Biometrics» more  HICSS 1995»
14 years 2 months ago
HINT: A new way to measure computer performance
The computing community has long faced the problem of scientifically comparing different computers and different algorithms. When architecture, method, precision, or storage capac...
John L. Gustafson, Quinn Snell
ARITH
1999
IEEE
14 years 3 months ago
Reduced Latency IEEE Floating-Point Standard Adder Architectures
The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the s...
Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, C...