Reduced Latency IEEE Floating-Point Standard Adder Architectures

The design and implementation of a double precision floating-point IEEE-754 standard adder is described which uses "flagged prefix addition" to merge rounding with the significand addition. The floating-point adder is implemented in 0:5m CMOS, measures 1:8mm2, has a 3-cycle latency and implements all rounding modes. A modified version of this floating-point adder can perform accumulation in 2-cycles with a small amount of extra hardware for use in a parallel processor node. This is achieved by feeding back the previous un-normalised but correctly rounded result together with the normalisation distance. A 2-cycle latency floating-point adder architecture with potentially the same cycle time that also employs flagged prefix addition is described. It also incorporates a fast prediction scheme for the true subtraction of significands with an exponent difference of 1, with one less adder. Key Words: floating-point, adder, arithmetic, VLSI.

• Type: Conference
• Year: 1999
• Where: ARITH
• Authors: Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, Cheng-Chew Lim
• Keywords: Applied Computing, ARITH 1999, Flagged Prefix Addition, Floating-point Adder, Latency Floating-point Adder