522 search results - page 49 / 105 » A Note on Designing Logical Circuits Using SAT |
CHARME
2005
Springer
14 years 29 days ago
2005
Springer
Today, verification is becoming the dominating factor for successful circuit designs. In this context formal verification techniques allow to prove the correctness of a circuit ...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
The continuous minituarization of integrated circuits may reach atomic scales in a couple of decades. Some researchers have already built simple computation engines by manipulatin...
ENTCS
2006
13 years 7 months ago
2006
A compiler that automatically translates recursive function definitions in higher order logic to clocked synchronous hardware is described. Compilation is by mechanised proof in t...
DAC
1995
ACM
13 years 11 months ago
1995
ACM
Retiming has been proposed as an optimizationstep forsequential circuits represented at the net-list level. Retiming moves the latches across the logic gates and in doing so chang...
FPGA
2010
ACM
14 years 4 months ago
2010
ACM
Monte Carlo based SSTA serves as the golden standard against alternative SSTA algorithms, but it is seldom used in practice due to its high computation time. In this paper, we acc...