Accelerating Monte Carlo based SSTA using FPGA

Monte Carlo based SSTA serves as the golden standard against alternative SSTA algorithms, but it is seldom used in practice due to its high computation time. In this paper, we accelerate Monte Carlo based SSTA using the FPGA platform. A simple dataflow pipeline technique will not work well due to the excessive usage of FPGA logic slices. We leverage the recently proposed pattern matching method to identify common circuit structures, and further use a mathematical programming based formulation to explore the trade-off between performance and logic slices consumption. The proposed design provides two orders of magnitude speedup compared to the CPU-based implementation. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles – Algorithms implemented in hardware. General Terms Algorithms, Design, Performance. Keywords FPGA, Monte Carlo, SSTA.

• Type: Conference
• Year: 2010
• Where: FPGA
• Authors: Jason Cong, Karthik Gururaj, Wei Jiang, Bin Liu, Kirill Minkovich, Bo Yuan, Yi Zou
• Keywords: FPGA 2010, FPGA Logic Slices, Hardware, Logic Slices Consumption, Monte Carlo