522 search results - page 69 / 105 » A Note on Designing Logical Circuits Using SAT |
ASYNC
2000
IEEE
14 years 14 days ago
2000
IEEE
Fault Abstraction and Collapsing Framework for Asynchronous Circuits Philip P. Shirvani, Subhasish Mitra Center for Reliable Computing Stanford University Stanford, CA Jo C. Eberge...
ICCD
2005
IEEE
14 years 5 months ago
2005
IEEE
Traditional approaches for sequential logic optimization include (1) explicit state-based techniques such as state minimization, (2) structural techniques such as retiming, and (3...
CASES
2008
ACM
13 years 10 months ago
2008
ACM
We introduce the first approach that can actively control multiple hardware intellectual property (IP) cores used in an integrated circuit (IC). The IP rights owner(s) can remotel...
ISVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of e...
TCAD
2002
13 years 7 months ago
2002
We develop a general methodology to analyze crosstalk effects that are likely to cause errors in deep submicron high speed circuits. We focus on crosstalk due to capacitive coupli...