522 search results - page 81 / 105 » A Note on Designing Logical Circuits Using SAT |
DELTA
2004
IEEE
13 years 11 months ago
2004
IEEE
Complex arithmetic computations, especially if derived from bit-level software descriptions, can be very inefficient if implemented directly in hardware (e.g., by translation of t...
ARITH
2011
IEEE
12 years 8 months ago
2011
IEEE
— This paper presents a number of new high-radix ripple-carry adder designs based on Ling’s addition technique and a recently-published expansion thereof. The proposed adders a...
FPGA
2007
ACM
14 years 2 months ago
2007
ACM
We present an architecture for a synthesizable datapathoriented Field Programmable Gate Array (FPGA) core which can be used to provide post-fabrication flexibility to a Systemon-...
CF
2005
ACM
13 years 10 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...
ARVLSI
1997
IEEE
14 years 7 days ago
1997
IEEE
The growing gap between on-chip gates and off-chip I/O bandwidth argues for ever larger amounts of on-chip memory. Emerging portable consumer technology, such as digital cameras, ...