A synthesizable datapath-oriented embedded FPGA fabric

We present an architecture for a synthesizable datapathoriented Field Programmable Gate Array (FPGA) core which can be used to provide post-fabrication flexibility to a Systemon-Chip (SoC). Our architecture is optimized for bus-based operations that are common in signal processing and computation intensive applications. It employs a directional routing architecture, which allows it to be synthesized using standard ASIC design tools and flows. We also describe a proof-of-concept layout of our core. It is shown that the proposed architecture is significantly more area efficient than the best previously reported synthesizable programmable logic core. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles— Gate Arrays General Terms Design Keywords Field Programmable Gate Array, Datapath, Synthesis, Integrated Circuit, System-on-Chip, Embedded Block

• Type: Conference
• Year: 2007
• Where: FPGA
• Authors: Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton
• Keywords: Field Programmable Gate Array, FPGA 2007, Hardware, Synthesizable Datapathoriented Field, Synthesizable Programmable Logic