130 search results - page 10 / 26 » A Novel Metric for Interconnect Architecture Performance |
IPPS
2006
IEEE
14 years 1 months ago
2006
IEEE
The novel design of an efficient FPGA interconnection architecture with multiple Switch Boxes (SB) and hardwired connections for realizing data intensive applications (i.e. DSP ap...
CGO
2009
IEEE
14 years 2 months ago
2009
IEEE
Compilers employ many aggressive code transformations to achieve highly optimized code. However, because of complex target architectures and unpredictable optimization interaction...
VLSID
2007
IEEE
14 years 8 months ago
2007
IEEE
In this paper we explore the use of a set of novel design metrics for characterizing the impact of gate oxide tunneling current in nanometer CMOS devices and perform Monte Carlo s...
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology suc...
IEEEPACT
2007
IEEE
14 years 2 months ago
2007
IEEE
Nowadays, multithreaded architectures are becoming more and more popular. In order to evaluate their behavior, several methodologies and metrics have been proposed. A methodology ...