130 search results - page 20 / 26 » A Novel Metric for Interconnect Architecture Performance |
IPPS
2000
IEEE
13 years 11 months ago
2000
IEEE
In this paper, we propose a novel hardware caching technique, called switch directory, to reduce the communication latency in CC-NUMA multiprocessors. The main idea is to implemen...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Current technology trends have led to the growing impact of both inter-die and intra-die process variations on circuit performance. While it is imperative to model parameter varia...
ISCA
2007
IEEE
14 years 1 months ago
2007
IEEE
High availability is an increasingly important requirement for enterprise systems, often valued more than performance. Systems designed for high availability typically use redunda...
EUROPAR
2005
Springer
14 years 16 days ago
2005
Springer
Abstract. Blue Gene/L uses a large number of low power processors, together with multiple integrated interconnection networks, to build a supercomputer with low cost, space and pow...
FPL
2009
Springer
13 years 11 months ago
2009
Springer
In this paper we present a verification platform designed for HyperTransport 3.x (HT3) applications. HyperTransport 3.x is a very low latency and high bandwidth chip-tochip interc...