Sciweavers

1257 search results - page 34 / 252
» A Novel Sequencer Hardware for Application Specific Computin...
Sort
View
IEEEPACT
2008
IEEE
16 years 6 days ago
Meeting points: using thread criticality to adapt multicore hardware to parallel regions
We present a novel mechanism, called meeting point thread characterization, to dynamically detect critical threads in a parallel region. We define the critical thread the one with...
Qiong Cai, José González, Ryan Rakvi...
140
Voted
HPCA
2004
IEEE
16 years 6 months ago
Hardware Support for Prescient Instruction Prefetch
This paper proposes and evaluates hardware mechanisms for supporting prescient instruction prefetch--an approach to improving single-threaded application performance by using help...
Tor M. Aamodt, Paul Chow, Per Hammarlund, Hong Wan...
IPPS
2009
IEEE
16 years 13 days ago
Using hardware transactional memory for data race detection
Abstract—Widespread emergence of multicore processors will spur development of parallel applications, exposing programmers to degrees of hardware concurrency hitherto unavailable...
Shantanu Gupta, Florin Sultan, Srihari Cadambi, Fr...
GECCO
2007
Springer
268views Optimization» more  GECCO 2007»
15 years 12 months ago
Synthesis of analog filters on an evolvable hardware platform using a genetic algorithm
This work presents a novel approach to filter synthesis on a field programmable analog array (FPAA) architecture using a genetic algorithm (GA). First, a Matlab model of the FPA...
Joachim Becker, Stanis Trendelenburg, Fabian Henri...
CODES
2008
IEEE
15 years 7 months ago
Profiling of lossless-compression algorithms for a novel biomedical-implant architecture
In view of a booming market for microelectronic implants, our ongoing research work is focusing on the specification and design of a novel biomedical microprocessor core targeting...
Christos Strydis, Georgi Gaydadjiev