In this paper, we have developed a HiTi (Hierarchical MulTi) graph model for structuring large topographical road maps to the minimum cost route computation. The HiTi graph model p...
Field-Programmable Gate Arrays (FPGAs) are being employed in high performance computing systems owing to their potential to accelerate a wide variety of long-running routines. Par...
Uday Bondhugula, Ananth Devulapalli, James Dinan, ...
For a weighted, undirected graph G = V;E where jVj = n and jEj = m, we examine the single most vital edge with respect to two measurements related to all-pairs shortest paths APSP....
This paper presents a general methodology for the efficient parallelization of existing data cube construction algorithms. We describe two different partitioning strategies, one f...
Frank K. H. A. Dehne, Todd Eavis, Susanne E. Hambr...
In the study of PetaFlop project, Processor-In-Memory array was proposed to be a target architecture in achieving 1015 floating point operations per second computing performance. ...
Yi Tian, Edwin Hsing-Mean Sha, Chantana Chantrapor...