36 search results - page 3 / 8 » A Parallel Algorithm for Minimum Cost Path Computation on Po... |
TKDE
2002
13 years 8 months ago
2002
In this paper, we have developed a HiTi (Hierarchical MulTi) graph model for structuring large topographical road maps to the minimum cost route computation. The HiTi graph model p...
FCCM
2006
IEEE
14 years 2 months ago
2006
IEEE
Field-Programmable Gate Arrays (FPGAs) are being employed in high performance computing systems owing to their potential to accelerate a wide variety of long-running routines. Par...
IPPS
1998
IEEE
14 years 23 days ago
1998
IEEE
For a weighted, undirected graph G = V;E where jVj = n and jEj = m, we examine the single most vital edge with respect to two measurements related to all-pairs shortest paths APSP....
ICDT
2001
ACM
14 years 29 days ago
2001
ACM
This paper presents a general methodology for the efficient parallelization of existing data cube construction algorithms. We describe two different partitioning strategies, one f...
IPPS
1998
IEEE
14 years 23 days ago
1998
IEEE
In the study of PetaFlop project, Processor-In-Memory array was proposed to be a target architecture in achieving 1015 floating point operations per second computing performance. ...