FCCM 2006 - PDF Preprint Papers

FCCM 2006 Annual IEEE Symposium on Field-Programmable Custom Computing Machines

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FCCM
2006
IEEE

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General Architecture for Hardware Implementation of Genetic Algorithm

14 years 5 months ago

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Tatsuhiro Tachibana, Yoshihiro Murata, Naoki Shiba...

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Id	Views	Title	Status

1	404	General Architecture for Hardware Implementation of Genetic Algorithm
2	268	Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAs	claim
3	201	Hardware/Software Approach to Molecular Dynamics on Reconfigurable Computers	claim
4	195	A Parallel Hardware Architecture for fast Gaussian Elimination over GF(2)	claim
5	170	An Architecture for Efficient Hardware Data Mining using Reconfigurable Computing Systems	claim
6	162	Power Visualization, Analysis, and Optimization Tools for FPGAs	claim
7	144	Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA	claim
8	138	Efficient Hardware Generation of Random Variates with Arbitrary Distributions	claim
9	137	Single Pass, BLAST-Like, Approximate String Matching on FPGAs	claim
10	136	Pre-synthesis Queue Size Estimation of Streaming Data Flow Graphs	claim
11	133	A Field Programmable RFID Tag and Associated Design Flow	claim
12	133	A Scalable FPGA-based Multiprocessor	claim
13	131	Packet Switched vs. Time Multiplexed FPGA Overlay Networks	claim
14	127	Scalable Softcore Vector Processor for Biosequence Applications	claim
15	125	A Multithreaded Soft Processor for SoPC Area Reduction	claim
16	121	An FPGA Solution for Radiation Dose Calculation	claim
17	121	COPACOBANA A Cost-Optimized Special-Purpose Hardware for Code-Breaking	claim
18	120	FPGAs, GPUs and the PS2 - A Single Programming Methodology	claim
19	119	Integrating FPGA Acceleration into the Protomol Molecular Dynamics Code: Preliminary Report	claim
20	118	COMMA: A Communications Methodology for Dynamic Module Reconfiguration in FPGAs	claim
21	117	A Scalable Hybrid Regular Expression Pattern Matcher	claim
22	113	GraphStep: A System Architecture for Sparse-Graph Algorithms	claim
23	111	Pipelined Mixed Precision Algorithms on FPGAs for Fast and Accurate PDE Solvers from Low Precision Components	claim
24	111	A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer	claim
25	108	A Reconfigurable Distributed Computing Fabric Exploiting Multilevel Parallelism	claim
26	107	Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths	claim
27	106	Defect-Tolerant Nanocomputing Using Bloom Filters	claim
28	106	Scalable Hardware Architecture for Real-Time Dynamic Programming Applications	claim
29	105	Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs	claim
30	101	A Type Architecture for Hybrid Micro-Parallel Computers	claim
31	100	Enabling a Uniform Programming Model Across the Software/Hardware Boundary	claim

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