36 search results - page 5 / 8 » A Parallel Algorithm for Minimum Cost Path Computation on Po... |
IPPS
2002
IEEE
14 years 1 months ago
2002
IEEE
In this paper we present new approaches to high performance protein database scanning on two novel massively parallel architectures to gain supercomputer power at low cost. The ...
ARC
2008
Springer
13 years 10 months ago
2008
Springer
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
IEEEPACT
2003
IEEE
14 years 1 months ago
2003
IEEE
This paper discusses a register bank assignment problem for a popular network processor--Intel's IXP. Due to limited data paths, the network processor has a restriction that ...
IEEEPACT
2005
IEEE
14 years 2 months ago
2005
IEEE
Scratchpad memory (SPM), a fast software-managed onchip SRAM, is now widely used in modern embedded processors. Compared to hardware-managed cache, it is more efficient in perfor...
PPOPP
2005
ACM
14 years 2 months ago
2005
ACM
We want to perform compile-time analysis of an SPMD program and place barriers in it to synchronize it correctly, minimizing the runtime cost of the synchronization. This is the b...