Sciweavers

471 search results - page 20 / 95
» A Parallel Hardware Architecture for Image Feature Detection
Sort
View
IPPS
1999
IEEE
14 years 28 days ago
Scalable Hardware-Algorithms for Binary Prefix Sums
Abstract. Themain contributionof thiswork isto propose a numberof broadcastefficient VLSI architectures for computing the sum and the prefix sums of a w k-bit, k 2, binary sequenc...
Rong Lin, Koji Nakano, Stephan Olariu, Maria Crist...
CATA
2003
13 years 10 months ago
A Programmable Logic-Based Implementation of Ultra-Fast Parallel Binary Image Morphological Operations
Binary morphological operations are a building block in many computer vision applications. Several iterative morphological operations are commonly performed for image analysis res...
Songpol Ongwattanakul, Phaisit Chewputtanagul, Dav...
SIGGRAPH
1999
ACM
14 years 29 days ago
A Real-Time Low-Latency Hardware Light-Field Renderer
This paper describes the design and implementation of an architecture for interactively viewing static light fields with very low latency. The system was deliberately over enginee...
Matthew J. P. Regan, Gavin S. P. Miller, Steven M....
SI3D
2006
ACM
14 years 2 months ago
Hardware accelerated multi-resolution geometry synthesis
In this paper, we propose a new technique for hardware accelerated multi-resolution geometry synthesis. The level of detail for a given viewpoint is created on-the-fly, allowing f...
Martin Bokeloh, Michael Wand
ICPR
2002
IEEE
14 years 9 months ago
A Neural Architecture for Fast and Robust Face Detection
In this paper, we present a connectionist approach for detecting and precisely localizing semi-frontal human faces in complex images, making no assumption about the content or the...
Christophe Garcia, Manolis Delakis