Sciweavers

471 search results - page 41 / 95
» A Parallel Hardware Architecture for Image Feature Detection
Sort
View
ECBS
1996
IEEE
155views Hardware» more  ECBS 1996»
14 years 26 days ago
Model-Integrated Program Synthesis Environment
In this paper, it is shown that, through the use of Model-Integrated Program Synthesis MIPS, parallel real-time implementations of image processing data ows can be synthesized fro...
Janos Sztipanovits, Gabor Karsai, Hubertus Franke
SASP
2008
IEEE
183views Hardware» more  SASP 2008»
14 years 3 months ago
Application Acceleration with the Explicitly Parallel Operations System - the EPOS Processor
Different approaches have been proposed over the years for automatically transforming High-Level-Languages (HLL) descriptions of applications into custom hardware implementations. ...
Alexandros Papakonstantinou, Deming Chen, Wen-mei ...
ISCA
2012
IEEE
208views Hardware» more  ISCA 2012»
11 years 11 months ago
Harmony: Collection and analysis of parallel block vectors
Efficient execution of well-parallelized applications is central to performance in the multicore era. Program analysis tools support the hardware and software sides of this effor...
Melanie Kambadur, Kui Tang, Martha A. Kim
SI3D
2010
ACM
14 years 3 months ago
Parallel Banding Algorithm to compute exact distance transform with the GPU
We propose a Parallel Banding Algorithm (PBA) on the GPU to compute the exact Euclidean Distance Transform (EDT) for a binary image in 2D and higher dimensions. Partitioning the i...
Thanh-Tung Cao, Ke Tang, Anis Mohamed, Tiow Seng T...
ICIP
2005
IEEE
14 years 10 months ago
High throughput 2D DCT/IDCT processor for video coding
This paper describes the architecture of an 8x8 2-D DCT/IDCT processor with high throughput, reduced hardware, and a parallel-pipeline scheme. This architecture allows the process...
Gustavo A. Ruiz, Juan A. Michell, Angel M. Buron