High throughput 2D DCT/IDCT processor for video coding

This paper describes the architecture of an 8x8 2-D DCT/IDCT processor with high throughput, reduced hardware, and a parallel-pipeline scheme. This architecture allows the processing elements and arithmetic units to work in parallel at half the frequency of the data input rate. A fully pipelined row-column decomposition method based on two 1-D DCTs and a transpose buffer based on D-type flip-flops are used. The processor has been implemented in a 0.35-?m CMOS process with a core area of 3mm2

• Type: Conference
• Year: 2005
• Where: ICIP
• Authors: Gustavo A. Ruiz, Juan A. Michell, Angel M. Buron
• Keywords: ICIP 2005, Image Processing, Video Coding