471 search results - page 52 / 95 » A Parallel Hardware Architecture for Image Feature Detection |
VIS
2004
IEEE
14 years 10 months ago
2004
IEEE
We present a tool for real-time visualization of motion features in 2D image sequences. The motion is estimated through an eigenvector analysis of the spatiotemporal structure ten...
IEEEPACT
2008
IEEE
14 years 3 months ago
2008
IEEE
Communication overheads are one of the fundamental challenges in a multiprocessor system. As the number of processors on a chip increases, communication overheads and the distribu...
ISCAS
2003
IEEE
14 years 2 months ago
2003
IEEE
Spatial image processing chips, known as silicon retinas, are based on the architecture of vertebrate retina and can be mathematically represented as the Laplacian of Gaussian (LO...
ICCD
2000
IEEE
14 years 5 months ago
2000
IEEE
We introduce a new register file architecture that provides both row-wise and column-wise accesses, thus allowing partitioned instructions to be used in columnwise processing with...
IPPS
2010
IEEE
13 years 6 months ago
2010
IEEE
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...