471 search results - page 66 / 95 » A Parallel Hardware Architecture for Image Feature Detection |
132
Voted
FPGA
2006
ACM
15 years 7 months ago
2006
ACM
In this paper, we present reconfigurable hardware architecture for detecting semantics of streaming data on 1+ Gbps networks. The design leverages on the characteristics of contex...
140
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TOMACS
1998
15 years 3 months ago
1998
architectures at multiple levels of abstraction, encompassing both hardware and software. It has five modes of operation (Design, Model Validation, Build Simulation, Simulate Syste...
185
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LCPC
2009
Springer
15 years 8 months ago
2009
Springer
Programming heterogeneous parallel computer systems is notoriously difficult, but MIMD models have proven to be portable across multi-core processors, clusters, and massively paral...
160
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ICRA
2010
IEEE
15 years 1 months ago
2010
IEEE
— The latency of a perception system is crucial for a robot performing interactive tasks in dynamic human environments. We present MOPED, a fast and scalable perception system fo...
126
Voted
IPPS
2006
IEEE
15 years 9 months ago
2006
IEEE
This paper presents the hardware architecture of DynaCORE, a dynamically reconfigurable system-on-chip for network applications. DynaCORE is an application specific coprocessor ...