471 search results - page 66 / 95 » A Parallel Hardware Architecture for Image Feature Detection |
FPGA
2006
ACM
14 years 10 days ago
2006
ACM
In this paper, we present reconfigurable hardware architecture for detecting semantics of streaming data on 1+ Gbps networks. The design leverages on the characteristics of contex...
TOMACS
1998
13 years 8 months ago
1998
architectures at multiple levels of abstraction, encompassing both hardware and software. It has five modes of operation (Design, Model Validation, Build Simulation, Simulate Syste...
LCPC
2009
Springer
14 years 1 months ago
2009
Springer
Programming heterogeneous parallel computer systems is notoriously difficult, but MIMD models have proven to be portable across multi-core processors, clusters, and massively paral...
ICRA
2010
IEEE
13 years 7 months ago
2010
IEEE
— The latency of a perception system is crucial for a robot performing interactive tasks in dynamic human environments. We present MOPED, a fast and scalable perception system fo...
IPPS
2006
IEEE
14 years 2 months ago
2006
IEEE
This paper presents the hardware architecture of DynaCORE, a dynamically reconfigurable system-on-chip for network applications. DynaCORE is an application specific coprocessor ...