168 search results - page 17 / 34 » A Parameterized Architecture Model in High Level Synthesis f... |
APCSAC
2006
IEEE
14 years 1 months ago
2006
IEEE
In the ubiquitous era, it is necessary to research the architectures of multiprocessor system with high performance and low power consumption. A simulator developed in high level l...
ARCS
2004
Springer
13 years 11 months ago
2004
Springer
: This paper reports ongoing work towards a dynamically reconfigurable System-on-Chip (SoC) platform for video signal processing. It consists of dedicated, statically and dynamical...
TPDS
2002
13 years 7 months ago
2002
One of the most fundamental problems automatic parallelization tools are confronted with is to find an optimal domain decomposition for a given application. For regular domain prob...
ICASSP
2011
IEEE
12 years 11 months ago
2011
IEEE
In this paper, based on the proposed parallelization scheme of binary arithmetic decoding, a parallel AVC/H.264 context-based adaptive binary arithmetic coding (CABAC) decoder wit...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...