239 search results - page 44 / 48 » A Performance Evaluation of the Convex SPP-1000 Scalable Sha... |
PODC
2005
ACM
14 years 2 months ago
2005
ACM
In recent software transactional memory proposals, a contention manager module is responsible for ensuring that the system as a whole makes progress. A number of contention manage...
DSL
1997
13 years 10 months ago
1997
In this paper we describe our experience with Teapot [7], a domain-specific language for writing cache coherence protocols. Cache coherence is of concern when parallel and distrib...
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
IPPS
1999
IEEE
14 years 1 months ago
1999
IEEE
Clusters of workstations have emerged as a popular platform for parallel and distributed computing. Commodity high speed networks which are used to connect workstation clusters pr...
TC
2008
13 years 8 months ago
2008
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...