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IEEEPACT
2009
IEEE
13 years 4 months ago
Region Based Structure Layout Optimization by Selective Data Copying
As the gap between processor and memory continues to grow, memory performance becomes a key performance bottleneck for many applications. Compilers therefore increasingly seek to m...
Sandya S. Mannarswamy, Ramaswamy Govindarajan, Ris...
ISSTA
2004
ACM
14 years 4 days ago
An optimizing compiler for batches of temporal logic formulas
Model checking based on validating temporal logic formulas has proven practical and effective for numerous software engineering applications. As systems based on this approach ha...
James Ezick
IPPS
2002
IEEE
13 years 11 months ago
Effective Cross-Platform, Multilevel Parallelism via Dynamic Adaptive Execution
This paper presents preliminary efforts to develop compilation and execution environments that achieve performance portability of multilevel parallelization on hierarchical archit...
Walden Ko, Mark N. Yankelevsky, Dimitrios S. Nikol...
ICS
2007
Tsinghua U.
14 years 26 days ago
Optimization of data prefetch helper threads with path-expression based statistical modeling
This paper investigates helper threads that improve performance by prefetching data on behalf of an application’s main thread. The focus is data prefetch helper threads that lac...
Tor M. Aamodt, Paul Chow
IEEEPACT
1998
IEEE
13 years 11 months ago
A Matrix-Based Approach to the Global Locality Optimization Problem
Global locality analysis is a technique for improving the cache performance of a sequence of loop nests through a combination of loop and data layout optimizations. Pure loop tran...
Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanuja...