204 search results - page 26 / 41 » A Pipelined Memory Architecture for High Throughput Network ... |
IPPS
2008
IEEE
14 years 1 months ago
2008
IEEE
Our digital universe is growing, creating exploding amounts of data which need to be searched, protected and filtered. String searching is at the core of the tools we use to curb...
ASPLOS
1996
ACM
13 years 11 months ago
1996
ACM
This paper describes the synchronization and communication primitives of the Cray T3E multiprocessor, a shared memory system scalable to 2048 processors. We discuss what we have l...
PPOPP
2010
ACM
14 years 2 months ago
2010
ACM
In processors with several levels of hardware resource sharing, like CMPs in which each core is an SMT, the scheduling process becomes more complex than in processors with a singl...
IMC
2010
ACM
13 years 5 months ago
2010
ACM
Multi-core systems are the current dominant trend in computer processors. However, kernel network layers often do not fully exploit multi-core architectures. This is due to issues...
CF
2007
ACM
13 years 11 months ago
2007
ACM
This paper presents a novel architectural technique to hide fetch latency overhead of hardware encrypted and authenticated memory. A number of recent secure processor designs have...