204 search results - page 30 / 41 » A Pipelined Memory Architecture for High Throughput Network ... |
GLOBECOM
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract— Software routers are becoming an important alternative to proprietary and expensive network devices, because they exploit the economy of scale of the PC market and open...
TCAD
2010
13 years 2 months ago
2010
Abstract--This paper presents a GALS-compatible circuitswitched on-chip network that is well suited for use in many-core platforms targeting streaming DSP and embedded applications...
ISVLSI
2002
IEEE
14 years 14 days ago
2002
IEEE
We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NO...
CF
2006
ACM
14 years 1 months ago
2006
ACM
Packet processing systems maintain high throughput despite relatively high memory latencies by exploiting the coarse-grained parallelism available between packets. In particular, ...
FCCM
2004
IEEE
13 years 11 months ago
2004
IEEE
Searching for multiple string patterns in a stream of data is a computationally expensive task. The speed of the search pattern module determines the overall performance of deep p...