204 search results - page 37 / 41 » A Pipelined Memory Architecture for High Throughput Network ... |
ANCS
2007
ACM
13 years 11 months ago
2007
ACM
All-optical packet switching is a promising candidate for future high-speed switching. However, due to the absence of optical Random Access Memory, the traditional Virtual Output ...
CASES
2009
ACM
14 years 2 months ago
2009
ACM
Coarse-grained reconfigurable architectures (CGRAs) present an appealing hardware platform by providing programmability with the potential for high computation throughput, scalab...
ISCAPDCS
2007
13 years 9 months ago
2007
— Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have ...
ICS
2009
Tsinghua U.
14 years 2 months ago
2009
Tsinghua U.
Ethernet line rates are projected to reach 100 Gbits/s by as soon as 2010. While in principle suitable for high performance clustered and parallel applications, Ethernet requires ...
ICS
2005
Tsinghua U.
14 years 1 months ago
2005
Tsinghua U.
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...