Evaluation of architectural support for speech codecs application in large-scale parallel machines

— Next generation multimedia mobile phones that use the high bandwidth 3G cellular radio network consume more power. Multimedia algorithms such as speech, video transcodecs have very large instruction foot prints and consequently stalled due to instruction cache misses. The conflicts in on-chip caches contribute a large fraction of the CPU cycle penalty and hence increase in power consumption. Many commercial tools are developed to minimize such cache misses by adequately placing the frequently called procedures in an application. Followed by profile extraction, these tools use cache line coloring and post compilation techniques for cache hit optimization. The major impediment in the optimal performance of such tools is their static layout profile, which does not consider the dynamic behavior of the application. We propose a methodology called DCP (dynamic code placement) for positioning code at run time for good instruction cache performance and have implemented in high end processo...

• Type: Conference
• Year: 2007
• Where: ISCAPDCS
• Authors: Naeem Zafar Azeemi
• Keywords: Cache, Cache Hits, Distributed And Parallel Computing, Instruction Cache, ISCAPDCS 2007