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ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
14 years 7 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
ICCAD
2001
IEEE
144views Hardware» more  ICCAD 2001»
14 years 7 months ago
Faster SAT and Smaller BDDs via Common Function Structure
The increasing popularity of SAT and BDD techniques in verification and synthesis encourages the search for additional speed-ups. Since typical SAT and BDD algorithms are exponent...
Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah
SOSP
2003
ACM
14 years 7 months ago
User-level internet path diagnosis
Diagnosing faults in the Internet is arduous and time-consuming, in part because the network is composed of diverse components spread across many administrative domains. We consid...
Ratul Mahajan, Neil T. Spring, David Wetherall, Th...
CSCW
2010
ACM
14 years 7 months ago
Communication, collaboration, and bugs: the social nature of issue tracking in small, collocated teams
Issue tracking systems help organizations manage issue reporting, assignment, tracking, resolution, and archiving. Traditionally, it is the Software Engineering community that res...
Dane Bertram, Amy Voida, Saul Greenberg, Robert Wa...
CVPR
2010
IEEE
14 years 6 months ago
Toward Coherent Object Detection And Scene Layout Understanding
Detecting objects in complex scenes while recovering the scene layout is a critical functionality in many vision-based applications. Inspired by the work of [18], we advocate the ...
Yingze Bao, Min Sun, Silvio Savarese